An engineering position where I can apply my skills and talent to enhance company products and services whil challenging by desire to be creative.
Robert J. Sanders
SKILLS:
Hardware Analog and digital circuit design and development- signal processing amplifiers, integrators , phase lock loop circuits, filters, counters, multiplexers ; PC multilayer board design and layout using ORCAD , Mentor Graphics ( Design Architect), and PADS EDA tools. Proficient with LeCroy Serial Data Analyzer, logic analyzers, fourier analyzers, PCIe, PCI and VME bus architecture. PCB Component level research and derating – interfacing with vendors and suppliers .DDR2 memory interfacing and testing.
Embedded microprocessor based design- Renesas 2115, Intel Pentium III/ IV, Celeron 8051 , Motorola 68000/; USB interface , Ethernet10/100/1000 interface, RS232, RS485, SPI and I2C interface. JTAG testing. LED power management design and prototype.
MPC 860 ; Kiel/ Franklin, Microtek debugger for C. In Circuit Emulation tools.
Instructor - Teaching electronics to company technicians , customers and industrial technology students; generate course materials
Work Experience
April 06 to Nov 08 Hewlett-Packard - Vancouver Hardware Engineer
Design , Develop and test PCB Interface Board to Reflash printer logic PCBs and to update printer firmware . Use of Mentor Graphics Design Architect CAD for schematic capture. PADS for PCB layout . Integrate Renesas H8S2215R microcontroller with USB interface, LCD Display ,Flash memory and EPROMs.Use of VHDL and software to develop and test FPGA circuitry prototypes. Test Firmware. Derating analysis of copier prototype modules at component level.DDR2 memory testing. Test Bed development and testing of Copier Prototype Modules ( Chelan/ Buttercup, Chinook , Chippewa, Cowlitz ) using instrumentation ( O-scopes, digital voltmeters, IR cameras, simulated loads ) and environmental chambers. MALT testing of Chelan ,Chippewa, and Cowlitz modules. PCIe Compliance testing. Recommend circuit modifications based on testing and Derating analysis. LED power management design and prototype for Buttercup control interface.
7/2004 to 3/2006 Radisys Hardware Engineer Beaverton, OR. Redesign & document new microcontroller PCB motherboards ( Intel 815/ 845 Chipsets ) to meet RoHS compliancy. Research new RoHS compliant parts via interfacing with vendors/ suppliers. Lattice firmware development – ispLEVER . Resolve customer issues for Endura motherboards. Use of PADS EDA for PCB board layout.
6/2002 to 6/2004 OECO Hardware Design Engineer Milwaukie, OR.
PCB Board layout involving power supplies for F22 Raptor aircraft using ORCAD schematic capture and high current board layout. Aid in troubleshooting/ debug of power supplies.
6/2001 to 2/2002 NSI Leviton Hardware Engineer Tualatin, OR. Design / board layout of MPC 860 microcontroller with Ethernet interface as heart of design for lighting control for new PCB design .PADS for schematic capture and PCB layout. Document design theory. Firmware code development.
1/99 to 5/20001 PSC Scanning R&D Engineer Eugene, OR. Redesign and documentation of 4 slot dock motherboard to utilize 8031 master/ slave microcontroller with an IR port. Research new components via interfacing with vendors/ suppliers. Xilinx FPGA development. Use of Keil code debugger to write and verify firmware .
10/97 to 10 /98 Microtek International Applications Engineer Hillsboro, OR.
Customer Support of In Circuit Emulation ( ICE ) products - 8051, 80386/ 80486; PCI bus architechture , resolution of problems via phone and internet . Author and publish technical news letter for clients and in house use.
Electronic systems Design, Debug of Prototype systems . C Programming.
Course development and presentation to company field engineers – theory and troubleshooting
Transceiver maintenance and repair.
Analog / digital circuit prototype design and development. Amplifier design. Signal processing circuitry design - integrators, waveform generators , amplifiers , phase lock loop circuits.
ORCAD for schematic capture and PCB layout design
3/82 to 11/91 Arcata/ SSSC Scientific Support Lab
Title: Design Engineer Fort Hunter Ligett, CA. and North LasVegas, NV.
Nellis Network design upgrade to X.25 protocol.
Army C3I upgrades of throughput performance and cost of outmoded systems. Design/prototype of digital and analog circuits. Use of O-Scopes, logic analyzer VHDL and C programming . Prototype evaluation.
Hewlett Packard Work station; PCI and VME bus architecture.
9/84 to 3/85 Instructor – California Polytechnic University – San LuisObispo,CA.
Course Preparation Teaching – math, electronics theory and labs , counseling and grading of students– Industrial Technology Dept.
Education
Graduate work Electrical Engineering
California State University – Northridge, CA. 1976 -1978
Electrical Engineering
Oregon State University – Corvallis, OR 1970 - 1972
Graduate work Physics
Portland State University – Portland, OR. 1968 -1969
BS Physics / Graduate work Geophysics 1990 - 1992
University of Oregon – Eugene, OR. BS Physics June 1966
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