Summary • Hands-on experience in semiconductor process and device engineering, especially in NAND.
• Research and fabrication experience in advanced IC manufacturing processes and equipment.
• Experience in the area of statistical process control using DOE and SPC software.
• A thorough background in testing and characterization techniques.
Education Rochester Institute of Technology, Rochester, NY - Microelectronic Engineering Department
Master of Science (December 2008) – GPA: 4.000 / 4.000
Bachelor of Science (May 2006) – GPA: 3.705 / 4.000
Experience SanDisk – Milpitas, CA
NAND Process Integration Engineer – January 2009 – Present
• Develops new or modified process formulations, defines processing or handling equipment requirements and specifications, and reviews processing techniques and methods applied in the manufacture, fabrication, and evaluation of semiconductors.
• Reviews product requirements with product staff in Japan to ensure compatibility of processing methods as well as comply and evaluate test data to determine appropriate limits and variables for process or material specifications.
Rochester Institute of Technology – Rochester, NY
Teaching Assistant (Silicon Processes / IC Technology) – Fall 2006 – December 2008
• Instructed the hands-on lab portion of the class and helped in developing lab curricula.
• Fabrication experience in advanced IC manufacturing processes with a background in electrical testing and characterization techniques.
• Implement PMOS, NMOS, CMOS and MEMS processes.
Research (under Dr. Karl Hirschman) (co-op) – Fall 2005 – December 2008
• High power application BJT / VDMOS devices (sponsor: Spectrum Devices, Hatfield, PA)
• TFT transistor development (sponsor: Corning, Inc.)
• Macroporous silicon sensors for chemical/biological detection and long-life special-use batteries
MEMS Process Module Development Team, RIT SMFL (co-op) – Fall 2003; Spring 2004
• Used Design of Experiment (DOE) to characterize and optimize PECVD tool AME P5000
• Obtained a low stress oxide/nitride growth recipe for AME P5000 tool
• Assisted the development team with oxide bridge process and micro-mirror process
Skills Certified Clean Room Operations/Tools:
Lithography- SSI/SVG Wafer Tracks, Canon i-line /GCA g-line/ and ASML 248-nm steppers, Karl Suss MA 150 Aligner
Thermal/Implant- Bruce Furnaces, AG610 RTP, Varian 350D Ion Implanter, Heraeus Vacuum Oven
PVD- CHA Evaporator, CVC Evaporator, CVC 601,
Plasma Etch- Branson Asher, Drytek Quad, LAM 490, LAM 4600
CVD- AME P5000, ASM LPCVD
Wet Etch/Clean- Different wet benches
Metrology- LEO SEM, Philips SEM, Leitz Microscope, CDE Resmap, Rudolph Ellipsometer, Tencor 364 Surfscan, Tencor P2 Profilometer, Tencor Spectramap
CMP- Strausbaugh, Westech 372
Parametrics- HP 4156/4145, Keithley Semiconductor Parameter Analyzers
Skills Continued Design, Modeling and Simulation Tools:
Mentor Graphics IC station, Silvaco Athena/Atlas (SUPREM), Prolith, Design Architect (VLSI), OSLO (optical system modeling), TRIM (ion implant modeling)
Statistical Process Control:
JMP for Design of Experiment (DOE), MINITAB for Statistical Process Control (SPC)
Computing:
Microsoft Office, Excel Visual Basic (VBA)
Foreign Language:
Fluent in Japanese
Relevant Courses Graduate:
Photovoltaic, Defect Reduction and Yield Enhancement, Microfluidics, SiGe and SOI Device Technology, Advanced Field Effect Transistor Devices, Semiconductor Process & Device Modeling, Quantum and Solid State Fundamental, Statistical Process Control (SPC)
Undergraduate:
MEMS, Microelectronics Manufacturing, Microlithography Materials and Process, Microlithography Systems, Integrated Circuit Processing, Thin Film Processes, Silicon Processes, Semiconductor Devices, Optics, VLSI Design, Design of Experiments (DOE), Integrated Circuit Technology, Electronics, Electro-Magnetic Field, Linear Systems, Circuits, Digital Systems
Project MS Thesis “Development, Fabrication, and Characterization of a Vertical-Diffused MOS Process for Power RF Applicationsâ€
Designed process steps to create a 50 V power VDMOS transistor structure using Silvaco ATHENA (SUPREM-IV) process simulation.
Presented the VDMOS transistors successfully fabricated and characterized at RIT (Dec 2008)
Pseudo-SUPREM:
Designed and developed a semiconductor process simulator in Visual Basic to accurately simulate semiconductor processes of implant, diffusion and characterize the profiles (March 2007)
Simulation of Gate Induced Drain Leakage (GIDL) Effect:
Investigated GIDL effects through simulation in Silvaco ATHENA and ATLAS (March 2007)
Twin-well CMOS:
Successfully fabricated and characterized a 2-μm CMOS as a part of the RIT Twin-well CMOS process at the RIT Semiconductor and Microsystems Fabrication Laboratory (SMFL). (September 2006 - December 2006)
Piezoresistive Cantilever Structure Pressure Sensor:
Created a piezoresistive pressure sensor at the RIT Semiconductor and Microsystems Fabrication Laboratory during MEMS course. (September 2006 - December 2006)
Workfunction Tuning of Molybdenum Metal Gate by Nitrogen Incorporation
Senior Design Project investigating the Molybdenum Metal Gate work function tuning by the introduction of Nitrogen. (May 2006)
Review Papers:
Spreading Resistance Measurements Technique for Defect Reduction and Yield Enhancement Course – (November 2007)
Indium Phosphide Based Devices for SiGe and SOI Devices Course - (May 2007)
An Overview of Wafer Bonding for Microfluidics Course - (May 2007)
An Overview of Gate Induced Drain Leakage for Advanced FETs Course – (February 2007)
Awards Dean’s List – RIT (Fall 2001 – Winter 2002; Summer, Winter 2003; Fall/Winter 2004)
Institute Graduate Scholarship – RIT (2005-06, 2006-07)
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